Titanium disilicide (TiSi.sub.2) is commonly used as a salicide (Self-Aligned siLICIDE) material in state-of-the-art CMOS device processes. The salicide process is a key step in reducing the sheet resistance of the small dimension gate and source and drain (S/D) regions of a device. Keeping the sheet resistance of these regions low is critical to the operation of high performance CMOS devices and integrated circuits.
At the heart of the standard salicide process using TiSi.sub.2 is the formation of the C49 phase TiSi.sub.2 (i.e., high resistance state) from deposited titanium (Ti) and the subsequent transformation of this silicide to C54 phase TiSi.sub.2 (i.e., low resistance state). Traditionally, the formation is achieved with a second anneal following selective removal of unreacted Ti and titanium nitride (TiN).
In more detailed terms, a layer of Ti is deposited over the semiconductor structure. The layer is then subjected to a process to form a layer of C49 phase TiSi.sub.2, for example, an annealing process. When an annealing process is used, it is typically performed in a nitrogen ambient, so that the remaining non-silicided material is either unchanged or forms a metal nitride. A wet etch may then be used to selectively remove the non-silicided metal. In the case of Ti, a solution of H.sub.2 O.sub.2 and H.sub.2 O may be used to wet etch the TiN which is formed during the annealing process, thus, leaving a layer of C49 phase TiSi.sub.2. To initiate the C49 to C54 transformation, a second anneal is performed. To successfully transform, however, a sufficient number of C54 nucleation sites must be present in the TiSi.sub.2. If not enough sites are present, then there will be incomplete transformation of the silicide for the given anneal conditions.
This C49 to C54 nucleation phenomenon manifests itself in the "poly linewidth effect" where it is observed that it becomes increasingly more difficult to form low sheet resistance (C54 phase) TiSi.sub.2 on polysilicon lines having a width of less than about 1 .mu.m. As the dimensions of the gate shrink below this width, fewer and fewer C54 nucleation sites exist that can aid in the C49 to C54 transformation (e.g., when the dimension of the structure to be silicided is of the same order or smaller than the average distance between C54 nuclei).
This problem has been partially solved by introducing more C54 nucleation sites into the narrow polysilicon or silicon regions using ion implantation to "roughen" by damaging the surface of the material to be silicided. This approach, referred to as PAI (Pre-Amorphization Implantation), has been successfully demonstrated as being usable to obtain low sheet resistance TiSi.sub.2 on narrow (&lt;0.25 .mu.m) polysilicon lines. However, this approach suffers from the problem that the roughening/damaging created extends beyond the surface of the silicon and into the S/D regions of the device leads to increased diode junction leakage which degrades overall device performance.